1. Field of the Invention
The present invention relates to a communication system using a high speed downlink packet access (‘HSDPA’) scheme. More particularly, the present invention relates to an apparatus and a method for performing bit de-collection according to a hybrid automatic retransmission request (‘HARQ’).
2. Description of the Related Art
Voice data-centered mobile communication systems have evolved into wireless data packet communication systems providing data service and multimedia service of high quality at a high speed. Current standardization on a high speed downlink packet access (HSDPA) and a First Evolution Data Only (1xEV-DO) system progressed mainly by the 3GPP and the 3GPP2 is made by a representative effort to find out a solution for a high quality wireless data packet transmission service of high speed more than 2 Mbps in the 3G mobile communication system. The 4G mobile communication system has been developed with the aim of providing a high quality multimedia service of speed higher than that of the 3G mobile communication system.
Generally, the HSDPA scheme is the general term for a data transmission scheme including a high speed-downlink shared channel (‘HS-DSCH’), which is a downlink data channel, and control channels relating to the HS-DSCH for supporting high speed downlink packet data transmission in a universal mobile terrestrial system (UMTS) communication system. To support the HSDPA, an adaptive modulation and coding (‘AMC’) and a HARQ have been proposed.
In relation to the support of the HSDPA, the HARQ scheme denotes a predetermined link control scheme used for retransmitting a data packet to compensate for a data packet including an error when the error has occurred in the initially transmitted data packet. The HARQ scheme may be classified into a chase combining (‘CC’) scheme, a full incremental redundancy (‘FIR’) scheme and a partial incremental redundancy (‘PIR’) scheme.
The CC scheme is a scheme of simply retransmitting the same data packet as that which included an error in an initial transmission. A receiver combines the retransmitted data packet and the initially transmitted data packet having been stored in a reception buffer, thereby improving the reliability for a coding bit input to a decoder. Therefore, the entire performance gain of a system can be obtained. Herein, combining the same two data packets (i.e., the initially transmitted data packet and the retransmitted data packet) causes an effect similar to that of a repetition coding. Therefore, average performance gain effects of about 3 dB can be obtained.
The FIR scheme does not retransmit the same data packet as that including the error in the initial transmission, but transmits a data packet including only a redundancy bit generated in a channel coder. Therefore, the performance of the decoder in the receiver can be improved. That is, in decoding, the decoder uses not only information received in the initial transmission but also a recently received redundancy bit, thereby reducing a coding rate. Therefore, the performance of the decoder is improved.
Meanwhile, a transmission side of a node B does not differentiate a systematic bit from a parity bit which are data to be transmitted by means of the HARQ, but serializes and transmits the systematic bit and the parity bit. That is, the transmission side performs a bit collection for the systematic bit and the parity bit and transmits them to a reception side.
Then, the reception side must divide the input serialized data into the systematic bit and the parity bit. This is referred to as bit de-collection.
That is, a HARQ bit de-collection block receives a bit sequence deinterleaved according to each physical channel, divides the bit sequence into a systematic bit, a parity bit 1 and a parity bit 2, and sends the systematic bit, the parity bit 1 and the parity bit 2 to an inverse-rate matching block. Herein, the bit de-collection block includes a buffer and sequentially processes data received through each physical channel. Accordingly, the buffer has a capacity capable of storing all data received through the physical channel. For instance, one transport channel block can use 10 physical channels at a maximum in case of a HSDPA category 7. The sort of transport channel used by a user equipment (‘UE’) is classified into categories 1 to 10 according to the quantity of service data supporting the HSDPA. In the case of the category 7, 1400 bits at a maximum and about 7.2 Mbps can be processed during one transmission time interval (‘TTI’) of 2 ms. Further, in the case of the category 7, a UE must store the maximum number (i.e., 19200 bits) of bits for each TTI in order to combine retransmitted bits.
Herein, since each bit is expressed by a soft value of a 8Q-level, a bit de-collection buffer for storing the 19200 bits has a size of 8 (Q-level)×4 (row)×4800 (column)=153.6K. Hereinafter, a general bit de-collection buffer will be described with reference to FIG. 1.
FIG. 1 is a diagram illustrating the structure of the conventional bit de-collection buffer.
Referring to FIG. 1, the bit de-collection buffer sequentially inputs a deinterleaved bit sequence by four bits through a deinterleaver and performs a bit de-collection by the column. The buffer includes a parameter NROW representing the number of available rows and a parameter NCOL representing the number of available columns. Further, the buffer separately stores a systematic bit, a parity bit 1 and a parity bit 2, which are serialized and input, by means of a parameter NR representing the number of row occupied systematic and a parameter NC representing the number of column occupied systematic.
Herein, after performing the bit de-collection, the bit de-collection block outputs the bit sequence for which the bit de-collection has been performed to a rate matching block. If the rate matching block punctures a predetermined bit in matching the received bit sequences at a preset rate, the rate matching block repeats and outputs a bit, which is located at a puncture position, of the bit sequence output from the bit de-collection block. The repeated bit is subjected to a zero insertion in an input unit of the rate matching block. Accordingly, the address of an HARQ combination buffer storing the rate-matched bit sequence and the total number of the stored bits increase according to the number of bits punctured by the rate matching block. That is, the number of zero insertion bits increases according to the number of punctured bits and thus the total number of bits including the increased number of bits increases. Consequently, the number of addresses of the HARQ combination buffer also increases.
In contrast, when the rate matching block must repeat a predetermined bit in matching the received bit sequences at the preset rate, a combination occurs at a position at which the repetition is performed. Therefore, the entire number of addresses of the HARQ combination buffer and the number of stored bits are reduced as compared with the bit de-collection buffer.
FIG. 2 is a diagram illustrating a conventional process by which a systematic bit, a parity bit 1 and a parity bit 2 are assigned to a bit de-collection buffer.
Referring to FIGS. 2a to 2c, when a digital signal of two bits is transmitted according to a Quaternary Phase Shift Keying (QPSK) scheme, different types of write operations are performed by the parameters NR, NC, NCOL and NROW. That is, the NCOL represents the number of available columns of the bit de-collection buffer and the NROW representing the number of available rows of the bit de-collection buffer. Further, since two bits are used according to a QPSK scheme, the NROW has a value of 2. Further, the value 10 of the NCOL is a value having been set for convenience of description.
FIG. 2a illustrates a case in which the NR has a value of 0 and the NC has a value of 6. That is, since the NR has a value of 0 and the NC has a value of 6, the systematic bits are assigned from a first column to a sixth column of a first row. Accordingly, the systematic bits are assigned to addresses of [0, 4, 8, 12, 16, 20], the parity bits 2 are assigned to addresses of [1, 9, 17, 24, 28, 32, 36] and the parity bits 1 are assigned to addresses of [5, 13, 21, 25, 29, 33, 37].
FIG. 2b illustrates a case in which the NR has a value of 1 and the NC has a value of 0. That is, since the NR has a value of 1 and the NC has a value of 0, the systematic bits are assigned to a first row. Accordingly, the systematic bits are assigned to addresses of [0, 4, 8, 12, 16, 20, 24, 28, 32, 36], the parity bits 2 are assigned to addresses of [1, 9, 17, 25, 33] and the parity bits 1 are assigned to addresses of [5, 13, 21, 29, 37].
FIG. 2c illustrates a case in which the NR has a value of 1 and the NC has a value of 4. That is, since the NR has a value of 1 and the NC has a value of 4, the systematic bits are assigned from a first column of a first row to a fourth column of a second row. Accordingly, the systematic bits are assigned to addresses of [0, 1, 4, 5, 8, 9, 12, 13, 16, 20, 24, 28, 32, 36], the parity bits 2 are assigned to addresses of [17, 25, 33] and the parity bits 1 are assigned to addresses of [21, 29, 37].
Meanwhile, referring to FIGS. 2d to 2f, when a digital signal of four bits is transmitted according to a 16 Quadrature Amplitude Modulation (QAM) scheme, different types of write operations are performed by the parameters NR, NC, NCOL and NROW. That is, according to a 16 QAM scheme, the NROW has a value of 4 and the NCOL is set to 10 for convenience of description.
FIG. 2d illustrates a case in which the NR has a value of 0 and the NC has a value of 6. That is, since the NR has a value of 0 and the NC has a value of 6, the systematic bits are assigned from a first column to a sixth column of a first row. Accordingly, the systematic bits are assigned to addresses of [0, 4, 8, 12, 16, 20], the parity bits 2 are assigned to addresses of [1, 3, 6, 9, 11, 14, 17, 19, 22, 24, 26, 28, 30, 32, 34, 36, 38] and the parity bits 1 are assigned to addresses of [2, 5, 7, 10, 13, 15, 18, 21, 23, 25, 27, 29, 30, 33, 35, 37, 39].
FIG. 2e illustrates a case in which the NR has a value of 1 and the NC has a value of 0. That is, since the NR has a value of 1 and the NC has a value of 0, the systematic bits are assigned to a first row. Accordingly, the systematic bits are assigned to addresses of [0, 4, 8, 12, 14, 16, 20, 24, 28, 32, 36], the parity bits 2 are assigned to addresses of [1, 3, 6, 9, 11, 14, 17, 19, 22, 25, 27, 30, 33, 35, 38] and the parity bits 1 are assigned to addresses of [2, 5, 7, 10, 13, 15, 18, 21, 23, 26, 29, 31, 34, 37, 39].
FIG. 2f illustrates a case in which the NR has a value of 1 and the NC has a value of 4. That is, since the NR has a value of 1 and the NC has a value of 4, the systematic bits are assigned from a first column of a first row to a fourth column of a second row. Accordingly, the systematic bits are assigned to addresses of [0, 1, 4, 5, 8, 9, 12, 13, 16, 20, 24, 28, 32, 36], the parity bits 2 are assigned to addresses of [2, 6, 10, 14,17, 19, 22, 25, 27, 30, 33, 35, 38] and the parity bits 1 are assigned to addresses of [3, 7, 11, 15, 18, 21, 23, 26, 29, 31, 34, 37, 39].
As described above, the systematic bit, the parity bit 1 and the parity bit 2 are stored in the bit de-collection buffer by means of the parameters NR and NC. FIG. 3 shows the structure of hardware performing a read operation for the bit sequence (i.e., the systematic bit, the parity bit 1 and the parity bit 2) stored in the bit de-collection buffer.
FIG. 3 is a block diagram illustrating the structure of a conventional read address generator for performing a read operation and FIG. 4 is a diagram showing one example of a conventional bit de-collection buffer for which the read address generator of FIG. 3 performs a conventional read operation.
Referring to FIGS. 3 and 4, a number generator 301 generates addresses to which the received bit sequences are assigned in order to perform a read operation. That is, when the total 19200 bit sequences capable of being transmitted through one TTI are received, the number generator 301 generates 19200 read addresses.
The number generator 301 generates addresses of [0, 1, 4, 5, 8, 9, 12, . . . , 44, 45, 48, 49] to which the received bit sequences are assigned according to the bit de-collection buffer of FIG. 4. That is, the received bit sequences are assigned to the addresses of [0, 1, 4, 5, 8, 9, 12, . . . , 44, 45, 48, 49]. A MOD 303 outputs a signal for an input signal according to a corresponding modulation scheme. The output signal is 00, 01, 10 and 11 for one input bit. A current column checker 305 checks a current column during a read process. That is, the current column checker 305 performs a change to a new column each fourth address of the bit de-collection buffer and provides the position of the current column. In other words, the current column checker 305 increases (shifts) one column each fourth address and checks the current column.
An address detector 307 detects whether bits assigned to a current address are systematic bits, parity bits 1 or parity bits 2 by means of information on a row, to which the systematic bits can be maximally assigned according to a modulation scheme, from the MOD 303 and information on the current column from the current column checker 305. That is, the address detector 307 detects an address to which the systematic bits are assigned and addresses to which the parity bits 1 and the parity bits 2 are assigned by means of the parameters NR and NC and outputs the addresses to a multiplexer 309.
FIG. 4 illustrates a case in which the NR has a value of 1 and the NC has a value of 2. Since the NCOL has a value of 13 and the NROW (the number of rows capable of being maximally assigned according to a modulation scheme) has a value of 2, the systematic bits of the received bit sequences are assigned to addresses of [0, 1, 4, 5, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48], the parity bits 2 of the received bit sequences are assigned to addresses of [9, 17, 25, 33, 41, 49] and the parity bits 1 of the received bit sequences are assigned to addresses of [13, 21, 29, 37, 45].
The multiplexer 309 stores the addresses of [0, 1, 4, 5, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48] to which the systematic bits have been assigned in a register 311, stores the addresses of [13, 21, 29, 37, 45] to which the parity bit 1 has been assigned in a register 315, and stores the addresses of [9, 17, 25, 33, 41, 49] to which the parity bit 2 has been assigned in a register 313.
That is, the register 311 stores the addresses to which the systematic bits of the received bit sequences have been assigned, the register 313 stores the addresses to which the parity bit 1 of the received bit sequences have been assigned, and the register 315 stores the addresses to which the parity bit 2 of the received bit sequences have been assigned. The addresses of registers 311, 313 and 315 are multiplexed by multiplexer 317. Further, in performing the read operation, when a rate matching block performs a puncture for predetermined bits by a PUNC signal value, a Prev_REG 310 performs a read process by repeating and outputting the punctured bits from the multiplexer 319 which receives output signals from multiplexer 317 and Prev_REG 310.
For instance, when bits assigned to a first address and a fourth address are punctured, the read address generator repeats and generates the first address and the fourth address. Accordingly, the read address generator outputs addresses of [0, 1, 1, 4, 4, 5, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48] and performs a read operation. That is, even though the bits assigned to the first address and the fourth address are punctured, the read address generator repeats a previous bit to prevent an error from occurring.
A write address generator 321 sequentially inputs bit sequences, which have been deinterleaved by a deinterleaver (not shown), by four bits and performs a write operation. Herein, the bit sequences are classified into systematic bits, parity bits 1 and parity bits 2 by the bit de-collection parameters NR, NC, NCOL and NROW and written in corresponding addresses of the bit de-collection buffer. The process by which the corresponding bits are assigned to the corresponding addresses by each parameter is as described in FIG. 2.
When the read operation is performed as described above, the read address generator includes a separate register 311 for storing the addresses to which the corresponding systematic bits have been assigned. Further, the read address generator includes separate registers (registers 313 and 315) for storing the addresses to which the parity bit 1 and the parity bit 2 have been assigned.
Herein, since the maximum number of transmission bits transmitted for one TTI is 19200 bits, when one address of the bit de-collection buffer is stored in one register, the number of the addresses is 19200 at a maximum. Therefore, a 15 bit register capable of expressing 19200 addresses requires 19200 bits which is the total number of bits. Accordingly, the size of hardware increases and efficiency of power consumption decreases according to the increased size of the hardware.